1. Field of the Invention
The present invention relates to circuits used in communication equipment such as optical communication equipment and mobile communication equipment. These circuits include an optical receiving circuit, an optical transmitting circuit, an automatic gain control amplifier circuit, an automatic frequency compensation amplifier circuit, and a limiting amplifier circuit used for clock recovery. The invention relates in particular to an analog summing and differencing circuit used in a main amplifier and level discrimination circuit in the optical receiving circuit, in the part of the optical transmitting circuit that detects light emitted for monitoring purposes, in the amplitude-detecting part of the automatic gain control amplifier circuit and automatic frequency compensation amplifier circuit, and in a limiting amplifier, limit comparator, and offset compensator in the limiting amplifier circuit.
2. Description of the Related Art
As shown in FIG. 1, an optical receiving circuit includes a photodetector (PD), a preamplifier (P-Amp), n main amplifiers (M-Amp), where n is an integer equal to or greater than one, and a level discrimination circuit (L-Dis). The photodetector PD is reverse-biased by a voltage Vbias, and converts a received optical signal to a current signal Ip. The preamplifier converts the current signal Ip to a pair of differential voltages VAp, VAn. VAp is sometimes referred to as the non-inverting phase or positive phase, and VAn as the inverting phase, opposite phase, or negative phase, but the simpler terms positive voltage and negative voltage will be used for brevity below, with the understanding that they are merely convenient names and do not imply positive or negative algebraic values.
The n main amplifiers compensate for the direct-current (dc) offset of the differential voltages VAp, VAn, and amplify these voltages in n stages to a differential voltage level sufficient to drive the level discrimination circuit. The level discrimination circuit converts the final amplified differential voltages VCp(n), VCn(n) to a positive logic signal Qp and a negative logic signal Qn. The main amplifiers are described in, for example, U.S. Pat. Nos. 5,612,810, 5,875,049, and 5,892,609 (and corresponding Japanese Unexamined Patent Application Publications No. 08-84160, 09-289495, and 10-84231).
FIG. 49 shows the general structure of the main amplifier described in U.S. Pat. No. 5,612,810. This main amplifier includes an offset compensator 101a comprising an analog summing and differencing circuit (SUM/DIF CKT), and a differential amplifier Amp1. The offset compensator 101a includes a pair of peak-hold circuits PH1, PH2 and a pair of adders ADD1, ADD2. The adders ADD1, ADD2 constitute the summing and differencing part of the circuit. FIGS. 50 and 51 shows specific examples of the circuit configuration of the offset compensator 101a in FIG. 49.
In FIG. 49, peak-hold circuit PH1 senses the peak of the negative differential output voltage VAn of the preamplifier (cf. FIG. 1) and outputs a negative peak value VAnp; peak-hold circuit PH2 senses the peak of the positive differential output voltage VAp of the preamplifier and outputs a positive peak value VApp. Adder ADD1 outputs an offset-compensated positive differential voltage VBp by adding the positive differential voltage VAp and negative peak value VAnp; adder ADD2 outputs an offset-compensated negative differential voltage VBn by adding the negative differential voltage VAn and positive peak value VApp. The differential amplifier Amp1 amplifies the offset-compensated differential voltages VBp, VBn, and outputs a positive differential voltage VCp and a negative differential voltage VCn.
In the analog summing and differencing circuit in FIG. 50, adder ADD1 adds differential voltage VAp and peak value VAnp through a pair of summing resistors R2, R1 and outputs an offset-compensated positive differential voltage VBp; adder ADD2 adds differential voltage VAn and peak value VApp through a pair of summing resistors R3, R4 and outputs an offset-compensated negative differential voltage VBn.
If the resistance values of the summing resistors R1–R4 in FIG. 50 are related so that R1=R2 and R3=R4, the differential voltages VBp, VBn are given by the equations below.VBp=(VAnp+VAp)/2, VBn=(VAn+VApp)/2  (1)Accordingly, the adders ADD1, ADD2 can also be regarded as averaging circuits. Differencing is performed by supplying the outputs of adders ADD1, ADD2 to the differential inputs of the next-stage differential amplifier Amp1.
The analog summing and differencing circuit in FIG. 51 includes a balanced negative feedback amplifier Amp2 with a feedback resistor R5 connected between its inverting output and non-inverting input, and another feedback resistor R6 connected between its non-inverting output and inverting input. The positive differential voltage VAp and negative peak value VAnp are added through summing resistors R2, R1, and their sum becomes the non-inverting input of amplifier Amp2; the negative differential voltage VAn and positive peak value VApp are added through summing resistors R3, R4, and their sum becomes the inverting input of amplifier Amp2. The inverting output and non-inverting output of amplifier Amp2 are output as an offset-compensated positive differential voltage VBp and negative differential voltage VBn. The analog summing and differencing circuit in FIG. 51 replaces the adders ADD1, ADD2 in FIG. 49. Subtraction is performed by input to the differential input terminals of differential amplifier Amp1.
The main amplifier in FIG. 49 does not use negative feedback to compensate for offset, and is not affected by the relative rate of occurrence of ‘1’ and ‘0’ values, but can compensate for the differential dc offset voltage generated in the preamplifier, so stable operation and high gain can be obtained, even in a multistage configuration in which the last stage or stages perform a limiting operation.
In the main amplifier in FIG. 49, differential voltages VBp, VBn are related as indicated in the equation below.VBp−VBn=K((VAp+VAnp)−(VAn+VApp))  (2)
K in equation (2) is the gain (or attenuation ratio) in the analog summing and differencing circuit. The first term on the right indicates the value of VBp, the peak of which is the sum of the peak of pulse signal VAp and the peak-hold value VAnp (the peak value of pulse signal VAn). The second term on the right indicates the value of VBn, the peak of which is the sum of the peak of pulse signal VAn and the peak-hold value VApp (the peak value of pulse signal VAp). Subtraction of VBn from VBp means that these signals become differential inputs. The respective peak values of VBp and VBn are both equal to the sum of the peak values of the pulse signals VAp, VAn. Furthermore, since VAp and VAn are differential signals with identical amplitude, the amplitude values of VBp and VBn are identical. VBp and VBn therefore have the same peak value and amplitude, but are reversed in phase. Accordingly, VBp and VBn are offset-compensated differential signals.
FIG. 52 shows the general structure of the main amplifier described in U.S. Pat. No. 5,892,609. The reference voltage generator (REF-VOLTAGE-GEN) in this main amplifier has the same output dc voltage bias as the preamplifier (cf. FIG. 1). Input of the pair of peak-hold outputs VApp, VAnp to a differential input amplifier Amp2 with gain 0.5 produces a voltage VM in which one-half of the voltage offset of the differential voltages VAp, VAn is added to the output dc voltage bias, (corresponding to the median amplitude of the positive differential output VAp). This voltage VM then becomes a reference voltage VBn for the positive differential voltage VAp.
FIGS. 53 and 55 show the general structure of two main amplifiers described in U.S. Pat. No. 5,892,609, using like reference characters to indicate like elements. FIG. 54 shows a specific example of the circuit configuration of the offset compensator 101b in FIG. 53, comprising resistors R1–R6, bipolar transistors Q1–Q4, and constant-current sources Is1, Is2.
The main amplifiers in FIGS. 53 and 55 input an appropriate combination of the differential voltages VAp, VAn and peak-hold voltages VApp, VAnp to an amplifier with differential inputs and a wide input range (where widening the input range lowers the gain).
The main amplifier in FIG. 53 includes an offset compensator 101b comprising an analog summing and differencing circuit, and a differential amplifier Amp1. The offset compensator 101b includes a pair of peak-hold circuits PH1, PH2, a pair of amplifiers Gm1, Gm2 with differential voltage input and differential current output, and a pair of resistors R1, R2. The amplifiers Gm1, Gm2 and resistors R1, R2 constitute the summing and differencing part of the circuit.
Peak-hold circuit PH1 senses the peak of the negative differential voltage VAn from a preamplifier (cf. FIG. 1) and outputs a negative peak value VAnp; peak-hold circuit PH2 senses the peak of the positive differential voltage VAp from the preamplifier and outputs a positive peak value VApp. Amplifier Gm1 receives the positive differential voltage VAp from the preamplifier as its non-inverting input and the output VApp of peak-hold circuit PH2 as its inverting input, and outputs a positive differential current Io1p and negative differential current Io1n according to the differential input voltages VAp, VApp. Amplifier Gm2 receives the output VAnp of peak-hold circuit PH1 as its non-inverting input and the negative differential voltage VAn from the preamplifier as its inverting input, and outputs a positive differential current Io2p and negative differential current Io2n according to the differential input voltages VAnp, VAn. Resistor R1 converts the sum of the positive differential currents Io1p and Io2p to a positive output voltage VBp. Resistor R2 converts the sum of the negative differential currents Io1n and Io2n to a negative output voltage VBn. The differential amplifier Amp1 amplifies the offset-compensated positive output voltage VBp and negative output voltage VBn, and outputs a positive differential voltage VCp and a negative differential voltage VCn.
The main amplifier in FIG. 55 includes an offset compensator 101c comprising an analog summing and differencing circuit, and a differential amplifier Amp1. The offset compensator. 101c includes a pair of peak-hold circuits PH1, PH2, and a pair of amplifiers Din1, Din2 with differential voltage input and single-ended voltage output. The amplifiers Din1, Din2 constitute the summing and differencing part of the circuit.
Amplifier Din1 receives the positive differential voltage VAp from the preamplifier (cf. FIG. 1) as its non-inverting input and the output VApp of peak-hold circuit PH2 as its inverting input, and outputs a voltage VBp according to the differential input voltage. Amplifier Din2 receives the negative differential voltage VAn from the preamplifier as its non-inverting input and the output VAnp of peak-hold circuit PH1 as its inverting input, and outputs a voltage VBn according to the differential input voltage.
If differential input is regarded as subtraction and a T-network current sum is regarded as addition in FIGS. 53 and 55, then in FIG. 53, differential voltages VBp, VBn are related as indicated in the equation below.
                                                                        VBp                -                VBn                            =                              K                (                                                      (                                          VAp                      -                      VApp                                        )                                    +                                      (                                          VAnp                      -                      VAn                                        )                                                  )                                                                                        =                              K                (                                                      (                                          VAp                      +                      VAnp                                        )                                    -                                      (                                          VAn                      +                      VApp                                        )                                                  )                                                                        (        3        )            
In FIG. 55, differential voltages VBp, VBn are related as indicated in the equation below.
                                                                        VBp                -                VBn                            =                              K                (                                                      (                                          VAp                      -                      VApp                                        )                                    -                                      (                                          VAn                      -                      VAnp                                        )                                                  )                                                                                        =                              K                (                                                      (                                          VAp                      +                      VAnp                                        )                                    -                                      (                                          VAn                      +                      VApp                                        )                                                  )                                                                        (        4        )            
Equations (3) and (4) are the same as equation (2). Accordingly, VBp-VBn includes compensation for the dc offset of differential voltages VAp, VAn.
FIG. 56 shows the general structure of the level discrimination circuit described in U.S. Pat. No. 6,151,150 (and corresponding Japanese Unexamined Patent Application Publication No. 10-163828). This level discrimination circuit includes an offset compensator 104a comprising an analog summing and differencing circuit, and a comparator Comp1. The offset compensator 104a includes a pair of peak-hold circuits PH1, PH2, a pair of adders ADD1, ADD2, and a pair of voltage sources generating a reference voltage Vr and an offset voltage Voff. These circuit elements compensate for the dc offset of the differential voltages VCp, VCn and output differential voltages VEp, VEn. The adders ADD1, ADD2 constitute the summing and differencing part of the circuit. The comparator Comp1 compares the differential voltages VEp, VEn, and outputs a positive logic signal Qp and a negative logic signal Qn (one of the two logic signals, either Qp or Qn, may be omitted).
Photoelectric current flows in the photodetector PD (cf. FIG. 1) when the photodetector PD receives ‘1’ data, and does not flow when the photodetector PD receives ‘0’ data or does not receive any optical signal. A period during which photoelectric current does not flow will be referred to below as an extinction period, and a period during which photoelectric current flows and ‘1’ data is received will be referred to as a light-receiving period.
If the offset compensator of the level discrimination circuit has the same general structure as the offset compensator of the main amplifier, when the same values of the differential voltages VAp, VAn continue over a long extinction period, the differential output voltages VCp, VCn, of the main amplifier and the differential output voltages VEp, VEn of the offset compensator of the level discrimination circuit are output with offset voltage compensation and zero amplitude, and are related as indicated in the equation below (where the tilde ‘˜’ indicates approximate equality).VCp−VCn˜VEp−VEn˜0
If VEp−VEn˜0 as in the above equation, output of the positive logic signal Qp and the negative logic signal Qn becomes indeterminate or unstable.
In the offset compensator 104a in FIG. 56, input of the offset voltage Voff to adder ADD2 enables compensation for the dc offset of the differential voltage signals VCp, VCn to take place without having the logic signals Qp, Qn become indeterminate or unstable during long-period extinction. That is, if VCp−VCn˜0 over a long extinction period, then VEn>VEp because of the offset voltage Voff, stabilizing the logic signals at Qp=‘0’, and Qn=‘1’.
FIG. 57 shows the general structure of an automatic gain control amplifier circuit (AGC amplifier circuit). This AGC amplifier circuit includes a variable gain amplifier 16a, a peak-hold circuit PH, and a gain control amplifier 26a. The variable gain amplifier 16a, the variable gain of which is externally controllable, amplifies an input voltage VF according to the controlled gain and outputs a voltage VG. The peak-hold circuit PH senses the peak value of this voltage and outputs the peak value VGp. The gain control amplifier 26a receives the peak-hold voltage VGp as its inverting input and a reference voltage Vr as its non-inverting input, and controls the gain of the variable gain amplifier according to the peak-hold voltage VGp.
In the AGC amplifier circuit in FIG. 57, when the amplitude level of the input voltage VF increases, the gain control amplifier 26a decreases the gain of the variable gain amplifier 16a, thereby maintaining the output voltage VG of the variable gain amplifier 16a at a constant amplitude level, even if the amplitude level of the input voltage VF varies.
FIG. 58 shows the general structure of an automatic frequency compensation amplifier circuit (√f-AGC amplifier circuit), using the same reference characters as in FIG. 57 for similar elements. This √f-AGC amplifier circuit includes a variable frequency characteristic amplifier 17a, a peak-hold circuit PH, and an equalization characteristic control amplifier 27a. The variable frequency characteristic amplifier 17a amplifies an input voltage VF according to an externally controllable gain-frequency characteristic, and outputs a voltage VG. The equalization characteristic control amplifier 27a receives the peak-hold voltage VGp as its inverting input and a reference voltage Vr as its non-inverting input, and controls the gain-frequency characteristic of the variable frequency characteristic amplifier 17a according to the peak-hold voltage VGp.
When a pulse signal is transmitted on a (metallic) cable, if the cable is long, high frequency components are attenuated with what is generally termed a √f characteristic, degrading the pulse waveform. It is necessary to compensate by varying the receiving frequency characteristic of the pulse receiving circuit according to the length of the cable (the gain at high frequencies must increase to compensate for the √f characteristic). This compensation process is also referred to as equalization.
In the √f-AGC amplifier circuit in FIG. 58, when the amplitude level of the input voltage VF decreases because of pulse waveform degradation, the equalization characteristic control amplifier 27a increases the high-frequency gain of the variable frequency characteristic amplifier 17a, thereby keeping its output voltage VG at a constant amplitude level and maintaining a fixed pulse waveform, even if the input voltage signal VF is degraded.
The √f characteristic compensation method, which controls the peak of the output voltage of a variable frequency characteristic amplifier as is done in the √f-AGC amplifier circuit in FIG. 58, is suitable for a signal with relatively few low-frequency components. Such signals are generated by balanced codes such as the alternate mark inversion (AMI) code illustrated in FIG. 41A, the code mark inversion (CMI) code illustrated in FIG. 41B, and the Manchester code illustrated in FIG. 41C.
FIGS. 59A and 59B show the general structure of two optical transmitter circuits. Each optical transmitter circuit includes a light-emitting element (laser diode) LD, a switching circuit CUR-SW, driving current generating circuits IP, IB, and a light emission control circuit 118.
FIG. 60 shows a specific example of the circuit configuration of the light emission control circuit 118. The light emission control circuit 118 includes a monitor photodetector PDM, a preamplifier, a reference voltage circuit, a peak-hold circuit PH, and a light emission control amplifier C-Amp. The preamplifier includes a pair of impedance elements Zp and a differential amplifier (DIFF-AMP). The differential amplifier DIFF-AMP includes a differential amplifying stage (D-AMP) with a pair of resistors R1, R2, a pair of bipolar transistors Q1, Q2, and a current source Is1, and a buffer stage (BUFF) with a bipolar transistor Q3 and a current source Is2. The reference voltage circuit includes a variable resistor R3, a bipolar transistor Q4, and a pair of current sources Is3, Is4. The impedance elements Zp convert current to voltage, as indicated in FIG. 59C
The light-emitting element LD emits light according to a driving pulse current Ip and driving bias current Ib, and transmits an optical signal. The monitor photodetector PDM converts a received monitor light signal from the light-emitting element LD to a monitor current signal. The preamplifier (which, like the preamplifier 16a in FIG. 57, may have externally controllable gain) converts the monitor current signal to a voltage VG. The peak-hold circuit PH senses the peak value of this voltage and outputs the peak value VGp.
In the optical transmitter circuit in FIG. 59A, the driving pulse current generating circuit IP generates a driving pulse current Ip according to a control voltage VC, and the driving bias current generating circuit IB feeds the light-emitting element LD a driving bias current Ib that is independent of the control voltage VC. The switching circuit CUR-SW switches the driving pulse current Ip on and off according to a transmit data signal D, and outputs the switched driving pulse current Ip to the light-emitting element LD. The light emission control amplifier C-Amp compares the peak value VGp with a reference voltage Vr and varies the light emission control voltage VC so as to decrease the driving pulse current Ip if VGp is greater than Vr, or increase the driving pulse current Ip if VGp is less than Vr.
In the optical transmitter circuit in FIG. 59B, the driving pulse current generating circuit IP generates a driving pulse current Ip independent of the control voltage VC, and the driving bias current generating circuit IB feeds the light-emitting element LD a driving bias current Ib according to the control voltage VC. The switching circuit CUR-SW switches the driving pulse current Ip on and off according to the transmission data signal D, and outputs the switched driving pulse current Ip to the light-emitting element LD. The light emission control amplifier compares the peak value VGp with a reference voltage Vr and varies the light emission control voltage VC so as to decrease the driving bias current Ib if VGp is greater than Vr, or increase the driving bias current Ib if VGp is less than Vr.
FIGS. 61 and 62 show the general structure of two limiting amplifier circuits included in a clock recovery circuit. The limiting amplifier circuit 119A in FIG. 61 includes m differential amplifiers Lim(1) to Lim(m) (where m is an integer equal to or greater than one), and a comparator Comp. The limiting amplifier circuit 119B in FIG. 62, which also performs duty cycle compensation, adds a duty compensation circuit to the limiting amplifier circuit 119A. The duty compensation circuit includes a pair of averaging circuits Me1, Me2, a differential amplifier Amp, a resistor Rt, and a capacitor Ct. The clock recovery circuit also includes a tuning tank (TANK) and, in FIG. 61, a capacitively coupled amplifier Dout that converts the single-ended output of the tuning tank to a differential signal.
FIG. 63 shows signal waveforms in the clock recovery circuit in FIG. 61. The tuning tank in the clock recovery circuit outputs a clock component signal (tank output signal T-out) synchronized to a tank driving trigger signal (T-trigger). The clock component signal T-out is a damped oscillation signal and has an approximate sine waveform. The clock component signal T-out has high amplitude when the tank driving trigger signal T-trigger drives the tank frequently, and low amplitude when the tank driving trigger signal T-trigger drives the tank infrequently.
In the clock recovery circuit in FIG. 61, the tank output signal is converted to differential voltages VSp(1), VSn(1) in the differential output amplifier Dout. These differential voltages VSp(1), VSn(1) are amplified and limited in the limiting amplifier circuit 119A, from which recovered clock signals (logic signals) Qp, Qn are produced. The m differential amplifiers Lim(1) to Lim(m) amplify and limit the differential voltages VSp(1), VSn(1) and output differential voltages VUp(m) (also denoted VSp(m+1)) and VUn(m) (also denoted VSn(m+1)). The comparator Comp compares voltage VSp(m+1) with voltage VSn(m+1), and converts VSp(m+1) and VSn(m+1) to the logic signals Qp, Qn.
In the limiting amplifier circuit 119B in FIG. 62, the averaging circuit Me1 senses the mean value Qpm of recovered clock signal Qp, and the averaging circuit Me2 senses the mean value Qnm of recovered clock signal Qn. The differential amplifier Amp receives the mean value Qpm as its non-inverting input and the mean value Qnm as its inverting input, and increases the bias voltage of the inverting input of the first differential amplifier Lim(1) if Qpm is greater than Qnm, or decreases the bias voltage if Qpm is less than Qnm, so as to compensate for variations in the duty cycle of the recovered clock signals Qp, Qn. The time constant of capacitor Ct and resistor Rt stabilizes the duty cycle compensation.
FIGS. 64A, 64B, and 64C show waveforms in a main amplifier. FIG. 64A shows waveforms of the differential voltages VAp, VAn output from the preamplifier. FIG. 64B shows waveforms of the offset-compensated differential voltages VBp, VBn. FIG. 64C shows waveforms in which high frequency components (noise components) have been removed from the waveforms in FIG. 64B by a low pass filter.
Photoelectric current flows in the photodetector PD (cf. FIG. 1) in the optical receiving circuit during light-receiving periods (while receiving ‘1’ data), and does not flow during extinction periods (while receiving ‘0’ data or no optical signal). The thermal current noise generated by the photodetector PD varies according to the current value, so the noise level is higher during the reception of ‘1’ data than during the reception of ‘0’ data. Accordingly, as shown in FIG. 64A, the waveforms of the differential voltages VAp, VAn output from the preamplifier include more output noise during the reception of ‘1’ data, when photoelectric current flows in the photodetector PD, than during the reception of ‘0’ data, when photoelectric current does not flow in the photodetector PD. The peak-hold voltages VApp, VAnp of the differential voltages VAp, VAn therefore appear to be significantly greater than the true peak values when ‘1’ data is received, because a relatively high noise amplitude is added to the true peak values, but VApp, VAnp are close to the true peak values when ‘0’ data is received and the noise amplitude is relatively low.
In the offset compensators in the main amplifiers discussed above, the differential voltages VAp, VAn shown in FIG. 64A and the peak-hold voltages VApp, VAnp of VAp and VAn are added and subtracted to perform offset compensation, producing the waveform shown in FIG. 64B. After the waveform in FIG. 64B is passed through a low pass filter and high frequency noise is removed, the waveform shown in FIG. 64C is obtained.
In the waveform in FIG. 64C, the signal level differs depending on whether ‘1’ or ‘0’ data is being received, because the dc offset corresponding to the apparent increase of the peak value due to noise persists unnecessarily even after the noise itself has been filtered out. As a result, the minimum light receiving performance is greatly degraded. It would be desirable to have an offset compensator that does not leave this unnecessary dc offset.
In particular, practical operation of the main amplifier in FIG. 52 is greatly restricted, because differential amplifier Amp2 must have the same output dc voltage bias as the preamplifier, and a single-stage differential input amplifier such as an npn transistor amplifier does not have a large output dynamic range in the direction in which the output potential is lower than the input bias voltage.
If the main amplifier in FIG. 52 is to be implemented in an integrated circuit (IC), it is easy to achieve ratio accuracy, such as equal gain, but it is difficult to ensure an absolute value such as gain=0.5. For IC implementation, it would also be desirable to reduce the power consumption of the amplifier in the offset compensator. Accordingly, for IC implementation, it would be desirable to have an offset compensator with low power consumption and with a circuit that is easy to fabricate.
Furthermore, in an optical receiving circuit including the main amplifier above, n main amplifiers must be dc-coupled, and in dc coupling a level shift circuit must be included to control the dc level, which varies in the main amplifiers. It would also be desirable to have an offset compensator that does not need this type of level shift circuit but can obtain a balanced differential signal even from a simple preamplifier, such as a capacitively coupled amplifier, in which the bias voltage varies depending on the ‘1’ to ‘0’ ratio.
In the offset compensator in the level discrimination circuit in FIG. 56, the summing and differencing part must receive two mutually offset reference voltages as inputs, and the power supply generating the offset voltage Voff must be floated. Furthermore, the adders ADD1, ADD2 must add and subtract three values, which significantly complicates the circuit configuration. Accordingly, it would be desirable to have a level discrimination circuit that does not need a reference voltage and has a simpler circuit configuration.
In the conventional optical receiving circuits described above, dc offset is compensated in the offset compensators of the main amplifiers, so that the ‘1’ and ‘0’ pulse widths in the outputs Qp, Qn of the comparator in the level discrimination circuit do not differ (pulse intervals of one type are not longer than pulse intervals of the other type), while in the offset compensator of the level discrimination circuit described above, an offset voltage Voff is added to maintain Qp=‘0’, and Qn=‘1’ during extinction periods. Addition of this offset voltage, however, reduces the effect of offset compensation in the offset compensators in the main amplifiers. Accordingly, it would also be desirable to have a level discrimination circuit that does not require the addition of an offset voltage Voff and can thus avoid degradation of the time-slot width ratio of the comparator outputs Qp, Qn.
In general, the output of an amplifier is the combination of a dc bias component with a signal amplitude component, and the dc bias component varies with variations in the temperature and power supply. In the AGC amplifier circuit in FIG. 57, the peak value of the combined sum of the dc bias component and the signal amplitude component is sensed, so control of the signal amplitude is inaccurate and a constant amplitude cannot easily be maintained. Accordingly, it would be desirable to have an AGC amplifier circuit that senses and controls only the magnitude of the amplitude component.
For the same reason, it is difficult to compensate accurately for frequency characteristics in the √f-AGC amplifier circuit in FIG. 58. Accordingly, it would be desirable to have a √f-AGC amplifier circuit that senses and controls only the magnitude of the amplitude component.
In the light emission control circuits in FIGS. 59A and 59B, the dc level of the preamplifier output varies according to the temperature and the power supply. In the specific example of the circuit configuration of the light emission control circuit 118 in FIG. 60, the preamplifier includes a differential amplifier, and the reference voltage Vr input to the light emission control amplifier is generated by a circuit analogous to the differential amplifier, so variations in the dc level of the preamplifier output are compensated for by similar variations in the reference voltage Vr, both variations being caused by the same temperature and power supply variations. Even this circuit configuration, however, cannot remove the effect of the offset voltage generated in the differential amplifier, so light emission control fails to keep the amplitude of the light emission constant. Accordingly, it would be desirable to have a light emission control circuit that can accurately maintain a constant light emission amplitude in an optical signal.
In the limiting amplifier circuit 119A in FIG. 61, each differential amplifier Lim(1)−Lim(m) is a potential source of dc offset. This has little adverse effect on the ‘1’ and ‘0’ duty cycle of the output if the input to each differential amplifier has a large amplitude and the differential amplifier operates as a switching element, but if the input has a small amplitude and the differential amplifier operates as an active amplifier, the ‘1’ and ‘0’ duty cycle of the output is degraded according to the ratio of the magnitude of the input and the magnitude of the above offset (cf. FIG. 63). That is, the degree of degradation of the ‘1’ and ‘0’ duty cycle of the output varies according to the number of the differential amplifiers Lim(1)−Lim(m) that operate as switching elements.
The limiting amplifier circuit 119B in FIG. 62 attempts to compensate for this offset and thereby mitigate the degradation of the output duty cycle. This circuit 119B functions effectively when all m differential amplifiers Lim(1)−Lim(m) operate as active amplifying elements. When a differential amplifier operates as a switching element due to high input amplitude, however, the difference between its risetime characteristic and falltime characteristic becomes a major factor degrading the ‘1’ and ‘0’ duty cycle of the output. The operation of the circuit 119B in FIG. 62 then becomes unstable, because it attempts to compensate for factors other than the risetime-falltime difference that causes the duty cycle degradation. Unstable operation may also occur if the feedback time constant (the product of capacitance Ct and resistance Rt) is too small. Jitter may occur if this time constant is too large, however, because variations in the tank output level (envelope) cannot be tracked. Accordingly, it would be desirable to have a limiting amplifier circuit that can avoid both unstable operation and jitter.